Design Verification Engineer

About the role

Join Cisco’s ASIC Verification team in Yerevan as a Design Verification Engineer. You will work on cutting‑edge ASIC projects, ensuring that digital designs meet the highest standards of reliability and functionality.

Key responsibilities

• Develop comprehensive test plans and robust SystemVerilog test benches for advanced ASIC designs.
• Collaborate with design, verification, and physical design teams to integrate and validate test logic throughout the implementation flow.
• Debug complex issues using tools such as DVE and Verdi, and create scripts to automate verification tasks.
• Refine verification strategies to maximize coverage and efficiency, including AI‑calibrated verification approaches.
• Contribute to the delivery of high‑quality, reliable products that drive Cisco’s technology roadmap.

Required profile

• Bachelor’s or Master’s degree in Electrical or Computer Engineering or a related field.
• At least 2 years of experience in design verification and test‑bench development.
• Strong analytical and problem‑solving abilities with a collaborative mindset.

Required skills

• SystemVerilog
• UVM (preferred)
• DVE and Verdi debugging tools
• Scripting in Tcl, Python, or Perl

What we offer

• Hybrid work model (four days onsite at Cisco’s Yerevan office).
• Opportunities to work with the latest verification methodologies and AI‑driven technologies.
• Continuous learning environment within a global, innovative company.