Senior ASIC Digital Design Engineer

About the role

Synopsys is seeking an experienced ASIC Digital Design Engineer to lead the development of UCIe Controller IP used in high‑performance computing, automotive and AI products. You will own the RTL implementation from micro‑architecture through synthesis‑ready code, ensuring timing, power and area targets are met across advanced process nodes.

Key responsibilities

• Design and verify RTL modules for UCIe Controller IP.
• Optimize designs for timing closure, power consumption and silicon area.
• Develop Python, Tcl and Perl scripts to automate design generation and flow integration.
• Collaborate with architecture, verification and physical design teams to resolve technical challenges.
• Participate in design reviews and contribute to methodology development.

Required profile

• 8+ years of ASIC digital design experience with production RTL ownership.
• Strong expertise in timing analysis, power optimization and synthesis across multiple nodes.
• Proven ability to balance performance, area and power trade‑offs while meeting schedule commitments.
• Effective communication across cross‑functional teams and data‑driven problem solving.

Required skills

• Verilog (expert level for timing‑critical designs).
• Python, Tcl and Perl scripting for design automation.
• Deep knowledge of synthesis, timing analysis and power optimization.
• Experience with high‑speed interfaces or controller IP (preferred).