ASIC Design Verification Engineer

About the role

The ASIC Design Verification Engineer will support cutting‑edge ASIC projects within Cisco’s Silicon One team, developing robust test benches and verification strategies to ensure high‑quality silicon for Cisco’s core networking products.

Key responsibilities

• Drive comprehensive test planning and develop robust SystemVerilog test benches for ASIC projects.
• Collaborate with design, verification and physical design teams to integrate and validate test logic throughout implementation.
• Identify and resolve technical issues using advanced debugging tools such as DVE and Verdi.
• Develop and refine verification strategies to achieve optimal coverage and efficiency.
• Contribute to delivering reliable, high‑performance silicon that advances Cisco’s technology portfolio.

Required profile

• Bachelor’s or Master’s degree in Electrical or Computer Engineering or a related field.
• At least 1 year of experience in ASIC design verification.
• Demonstrated experience in test planning based on complex design specifications.
• Proven expertise in test‑bench development using SystemVerilog.
• Hands‑on debugging experience with DVE and Verdi tools and proficiency in scripting (Tcl, Python or Perl).

Required skills

• SystemVerilog
• UVM
• DVE
• Verdi
• Tcl, Python, Perl scripting