ASIC Layout Engineer

About the role

Cisco is hiring an ASIC Layout Engineer to design and verify standard cells for its next-generation ASICs on FinFET and GAA nodes. The engineer builds high-performance cell layouts, takes them through clean physical verification and runs library QA checks before release, working closely with senior engineers and the circuit design, characterization and physical design teams.

Key responsibilities

• Design standard cell layouts: logic, high-drive, clock, level shifter, tap/boundary and specialty cells.
• Optimize cell layouts for density, performance, power, EM and manufacturability.
• Run physical verification and fix issues to clean signoff: DRC, LVS, antenna, ERC and extraction.
• Run library QA checks and resolve view mismatches across GDS, LEF, Liberty, NDM and CDL.
• Develop and maintain scripts for layout, verification and QA (Python, Tcl, SKILL).
• Support analog/mixed-signal layout work, extraction and netlist QA, and help prepare library releases.
• Debug block-level layout and verification issues with the physical design and STA teams.
• Take part in layout and QA reviews and contribute to methodology improvements.

Required profile

• Bachelor's degree plus 3 years, Master's degree plus 2 years, or PhD of related experience in Electrical Engineering, Computer Engineering or a related field.
• First-hand standard cell or custom layout experience on FinFET nodes such as TSMC 7nm, 5nm, 3nm or 2nm.
• Experience with physical verification and extraction tools such as Calibre, ICV, StarRC or Quantus.
• Proficiency in Cadence Virtuoso.
• Strong written and spoken English, and experience working in multi-site teams.

Preferred qualifications

• Analog/mixed-signal design and layout experience (PLLs, LDOs, bandgaps, IOs, sensors, matching, shielding, post-layout simulation).
• Standard cell characterization and Liberty modeling (PrimeLib, Liberate, SiliconSmart).
• Library QA and view consistency checks, and library release workflows (abstract/LEF and NDM generation in P&R tools).
• Scripting in Python, Tcl, SKILL or Perl for design automation.
• Familiarity with EM/IR analysis and low-power cells (multi-Vt, power gating, retention).