ASIC Physical Design Engineer

About the role

Join Cisco's ASIC Physical Design Team to drive silicon innovation from RTL to GDSII. You will work closely with Front‑End teams to turn cutting‑edge designs into high‑performance, reliable silicon solutions.

Key responsibilities

• Implement macro‑level RTL to GDS flow and achieve sign‑off.
• Collaborate with Front‑End designers to ensure optimal physical implementation.
• Execute gate‑level netlist synthesis, floorplanning, placement, Clock Tree Synthesis (CTS) and routing.
• Optimize power, performance and area (PPA) while maintaining design integrity.
• Perform Static Timing Analysis, physical verification, formal verification and sign‑off closure.
• Analyze and resolve Electromigration (EM) and IR‑drop issues to meet reliability targets.

Required profile

• Bachelor's or Master's degree in Electrical Engineering, Computer Science or related field.
• Minimum 3 years of ASIC design and verification experience.
• Knowledge of block‑level synthesis, place‑and‑route and timing closure.
• Hands‑on experience with industry‑standard tools such as Synopsys and Cadence.

Required skills

• Synopsys EDA tools
• Cadence EDA tools
• Static Timing Analysis (STA)
• LVS and DRC verification techniques
• Scripting in Tcl, Python or Perl

What we offer

• Opportunity to shape future connectivity technology.
• Mentorship, career growth and a culture that celebrates success.
• Work at a leading company with 40 years of innovation in the AI era.