Layout Design Manager – Advanced SerDes & High‑Speed IP

About the role

You have built a career in custom analog and mixed‑signal layout, understanding that successful tapeouts depend on solid floor‑planning, rigorous verification, and proactive risk management. At Synopsys you will lead the layout organization responsible for advanced SerDes and high‑speed connectivity IP that defines industry standards.

Key responsibilities

• Lead and manage a layout engineering team delivering custom analog/mixed‑signal IC layout for PCIe Gen7/Gen8, UCIe, SerDes, PLLs, PHYs, and power‑management IP.
• Direct layout execution from floor‑planning through tape‑out, including resource planning, schedule management, and risk mitigation across concurrent programs.
• Establish and implement advanced layout methodologies, automation frameworks, and AI‑assisted design tools to improve quality and efficiency.
• Collaborate with analog design, digital implementation, verification, CAD, and product engineering to resolve technical challenges and ensure project alignment.
• Define and enforce layout standards for DRC, LVS, EMIR, reliability, ESD, and manufacturing compliance across advanced CMOS processes.
• Build organizational capability by recruiting, mentoring, and developing layout engineers and technical leads.

Required profile

• 10+ years of professional experience in custom analog/mixed‑signal IC layout with advanced CMOS technologies.
• 3+ years of experience managing and developing layout engineering teams.
• Proven track record delivering high‑speed SerDes, PLLs, PHYs, ADC/DACs, or power‑management circuits through multiple production tape‑outs.
• Strong ability to identify design‑for‑manufacturing issues, communicate mitigation strategies, and coach engineers.

Required skills

• Analog and mixed‑signal IC layout, floor‑planning, and tape‑out execution.
• Expertise in DRC, LVS, EMIR, reliability, ESD, and design‑for‑manufacturing requirements.
• Advanced CMOS process knowledge and automation/AI‑assisted layout tools.
• Experience with high‑speed interface standards such as PCIe Gen7/Gen8 and UCIe.
• Hands‑on knowledge of SerDes, PLLs, PHYs, ADC/DAC, and power‑management IP.