Senior Layout Engineer - SRAM Memory Macros

About the role

Synopsys, a leader in engineering solutions from silicon to systems, is looking for a Senior Layout Engineer to design and optimize full-custom SRAM memory macros in advanced technology nodes. The work covers memory IP that ships in real products, so layout decisions directly affect performance, yield and time to market.

Key responsibilities

• Design and implement full-custom layout for SRAM memory macros, from bitcell through array to peripheral circuits
• Optimize layouts for area, performance and power while keeping design rules and manufacturability in mind
• Run and resolve DRC, LVS, ERC, antenna, density and EM checks using Calibre, ICV and other verification tools
• Work with circuit designers to turn schematics into physical layouts that meet electrical and reliability specs
• Collaborate with process and foundry teams to apply technology files, design rules and device models
• Iterate on layout based on parasitic extraction results and post-layout simulation feedback

Required profile

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering or Microelectronics
• 1+ years of hands-on experience in SRAM or custom memory layout design
• Strong knowledge of SRAM architecture, memory circuits, custom layout techniques, matching, symmetry and device reliability
• Ability to work across time zones with global teams when needed

Required skills

• Cadence Virtuoso, Calibre, Custom Compiler and ICVS
• DRC/LVS closure, RC extraction and EM/IR considerations
• Advanced nodes (7nm, 5nm or below) is a plus

What we offer

A comprehensive range of health, wellness and financial benefits, including monetary and non-monetary offerings; salary range and further benefit details shared by the recruiter during the hiring process.