Staff Engineer – SRAM Layout Design

About the role

Synopsys is seeking an experienced Staff Engineer to lead physical layout development for embedded SRAM memory compiler peripheral circuits. You will work on advanced technology nodes, translating circuit intent into high‑quality silicon while ensuring performance, power, area, reliability and yield targets.

Key responsibilities

• Lead layout development for sense amplifiers, decoders, write drivers and control logic across advanced nodes.
• Optimize SRAM layouts for performance, power, area efficiency, manufacturability and yield.
• Drive physical verification closure (DRC, LVS, ERC, antenna checks, parasitic extraction) and resolve issues with CAD and verification teams.
• Collaborate with circuit designers to meet timing, matching and electrical requirements.
• Develop methodology improvements and automation to increase team productivity.
• Provide technical guidance, mentorship and design reviews for layout engineers.

Required profile

• 6+ years of professional SRAM or embedded memory layout experience, including bitcells, arrays and peripheral circuits.
• Strong analytical skills for device matching, parasitic management and advanced‑node design‑rule challenges.
• Proven ability to lead verification closure and work with foundry or technology bring‑up teams.
• Effective communication with circuit design teams and ownership of technical deliverables.

Required skills

• SRAM layout design
• Physical verification (DRC, LVS, ERC, antenna checks)
• Parasitic extraction
• Layout automation / scripting
• Advanced‑node design‑rule expertise
• Technology bring‑up and foundry collaboration