Senior Analog Design Engineer

About the role

We are seeking a Senior Analog Design Engineer to join a globally distributed team developing high‑speed DDR and SerDes IP in leading‑edge 7nm, 5nm and 3nm FinFET processes. The role focuses on core PHY blocks such as GDDR, PCIe, Ethernet and USB, delivering best‑in‑class performance for HPC and hyperscale data‑center markets.

Key responsibilities

• Design, pre‑layout and post‑layout verification of NRZ and PAM4 GDDR/SerDes circuits.
• Develop schematics, perform detailed layout reviews, and run comprehensive simulations.
• Optimize high‑speed paths for low jitter and low power consumption.
• Lead design reviews, create technical documentation and presentation slides.
• Provide guidance to validation engineers during bring‑up, debug and characterization of SerDes silicon.
• Collaborate on circuit trade‑off analysis and interpret system‑level specifications.

Required profile

• Strong understanding of analog/mixed‑signal design theory, including mismatch, linearity, stability, noise and low‑power techniques.
• Hands‑on experience with at least one high‑speed PHY component (CDR, PLL, PI, CTLE, TX driver, Serializer/Deserializer).
• Proven tape‑out record with silicon meeting performance and power targets.
• Ability to communicate technical issues clearly and present coherent design reviews.
• Experience with FinFET technologies (7nm/5nm/3nm) and high‑speed layout constraints.

Required skills

• Analog/mixed‑signal circuit design
• High‑speed DDR and SerDes IP
• PHY blocks: CDR, PLL, PI, CTLE, TX driver, Serializer/Deserializer
• NRZ and PAM4 signaling
• Chip tape‑out, silicon validation and debug
• Circuit simulation and verification tools
• Critical layout review in FinFET processes
• High‑speed ADC/DAC, VCO, clock distribution, equalizers (CTLE, FFE, DFE)