SOC Engineering Intern

About the role

Synopsys, a company that designs high-performance silicon chips, is looking for an SOC Engineering Intern. The intern joins a team focused on ASIC and SoC solutions and works alongside experts in RTL, STA, packaging and signoff. The internship offers hands-on experience on real projects with the freedom to share ideas and explore interests.

Key responsibilities

• Support chip-level physical design from netlist through final implementation (RTL to GDSII)
• Gain hands-on experience with floorplanning, placement, clock tree synthesis, routing and physical verification
• Assist with design optimization for timing, power, area and congestion
• Help debug design or flow issues under the guidance of senior engineers
• Contribute to the development and improvement of automation scripts and design methodologies
• Investigate and troubleshoot design, tool and flow issues throughout the implementation cycle
• Take part in technical discussions, reviews and knowledge-sharing sessions

Required profile

• Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Microelectronics or a related field
• Basic understanding of digital design, semiconductor fundamentals and/or ASIC design concepts
• Good written and verbal communication skills in English
• Eagerness to learn, collaborate and develop practical engineering skills

Required skills

• Familiarity with the ASIC physical design flow (floorplanning, placement, clock tree synthesis, routing, timing analysis) is a plus
• Exposure to EDA or physical design tools through coursework, university projects or previous experience is a plus
• Familiarity with scripting or programming languages such as TCL, Python or Perl is an advantage