Junior ASIC Physical Design Engineer

About the role

We are seeking a motivated Junior ASIC Physical Design Engineer to join our team developing next‑generation networking ASICs. This position is ideal for recent graduates or engineers with limited industry experience who want to build a career in semiconductor design and physical implementation.

Key responsibilities

• Support the full ASIC implementation flow, including synthesis, floorplanning, placement, clock‑tree synthesis, routing and timing closure.
• Perform basic static timing analysis and help resolve setup, hold and other timing violations.
• Analyze power, congestion and run physical verification checks.
• Execute physical design and sign‑off flows using industry‑standard EDA tools.
• Develop and maintain automation scripts in Python, Tcl, Shell or similar languages.
• Work with Verilog‑based designs and assist in debugging implementation issues.
• Collaborate with RTL, DFT, STA, verification, CAD and other engineering teams to meet project milestones.
• Document design progress, results and technical findings.

Required profile

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or a related field.
• Strong understanding of digital logic design and basic CMOS fundamentals.
• Basic knowledge of the ASIC design and implementation flow.
• Familiarity with Verilog or SystemVerilog.
• Understanding of timing concepts such as clocks, constraints, setup and hold.
• Experience with Linux or Unix environments and basic scripting skills.

Required skills

• Python
• Tcl
• Shell scripting
• Perl
• Verilog / SystemVerilog
• Linux / Unix
• Synopsys EDA tools
• Cadence EDA tools
• Siemens EDA tools