Layout Design Engineer

About the role

We are seeking a senior Layout Design Engineer with deep expertise in custom memory layout for advanced process nodes. You will translate SRAM circuit designs into manufacturable silicon, ensuring tight matching, symmetry, and parasitic‑optimized performance.

Key responsibilities

• Create custom layout for bit‑cell arrays, sense‑amp periphery, and decoder logic under advanced‑node design rules.
• Maintain tight matching and symmetry across critical circuit paths.
• Run and close DRC, LVS, and parasitic extraction using complex multi‑patterning or EUV rule decks.
• Collaborate with circuit designers to iterate floorplans and minimize parasitic impact on timing and power.
• Work directly with foundry or PDK teams on manufacturability, restrictive design rules, and process‑specific constraints.
• Support silicon debug by tracing layout‑related root causes of failures.

Required profile

• 8+ years of custom IC layout experience, specifically with SRAM or embedded memory on advanced nodes.
• Hands‑on experience with multi‑patterning or EUV design rule constraints.
• Strong command of DRC/LVS tools and custom layout editors at advanced nodes.
• Deep understanding of matching techniques and parasitic‑aware layout practices.
• Proven ability to meet aggressive area targets without sacrificing yield.

Required skills

• Custom IC layout
• SRAM layout
• Advanced process nodes
• Multi‑patterning
• EUV design rules
• DRC
• LVS
• Parasitic extraction
• Layout editors
• Matching techniques
• Parameterized layout scripting
• Memory compiler layout generation
• Advanced packaging
• 3D memory stacking