Layout Design Engineer

About the role

We are seeking a senior layout design engineer with deep expertise in custom memory layout for advanced process nodes. The role focuses on translating SRAM circuit designs into manufacturable, matched, and parasitic‑optimized silicon while navigating tight design rules and multi‑patterning/EUV constraints.

Key responsibilities

• Create custom layout for bit‑cell arrays, sense‑amp periphery, and decoder logic under advanced‑node design rules.
• Ensure tight matching and symmetry across critical circuit paths to mitigate variation‑induced mismatch.
• Run and close DRC, LVS, and parasitic extraction using complex multi‑patterning or EUV‑based rule decks.
• Collaborate with circuit designers to optimise floorplan and minimise parasitic impact on timing and power.
• Work directly with the foundry or PDK team on manufacturability, restrictive design rules, and process‑specific constraints.
• Support silicon debug by tracing layout‑related root causes of failures, including advanced‑node patterning issues.

Required profile

• 8+ years of custom IC layout experience, specifically SRAM or embedded memory on advanced nodes.
• Hands‑on experience with multi‑patterning or EUV design rule constraints.
• Strong command of DRC/LVS tools and custom layout editors at advanced nodes.
• Deep understanding of matching techniques and parasitic‑aware layout practices.
• Proven ability to close layout on aggressive area targets without compromising yield.

Required skills

• Custom IC layout
• SRAM/embedded memory layout
• Advanced process‑node design rules
• Multi‑patterning and EUV constraints
• DRC/LVS tools
• Custom layout editors
• Matching and symmetry techniques
• Parasitic extraction and analysis
• Parameterised layout scripting
• Memory compiler layout generation
• Advanced packaging / 3D memory stacking knowledge