Principal Engineer – ASIC Digital Design

About the role

Synopsys is seeking an experienced Principal Engineer to lead ASIC digital design verification. You will work on complex ASIC blocks and systems, ensuring they meet performance, power, and reliability targets.

Key responsibilities

• Lead verification of complex ASIC blocks and systems using UVM.
• Partner with design teams to define verification requirements and develop test plans.
• Build, maintain, and enhance UVM testbenches, agents, and verification environments.
• Apply SVA, formal verification, and coverage analysis to validate functionality and performance.
• Utilize advanced EDA tools to optimize design performance and power efficiency.
• Mentor junior engineers and promote best practices across the team.

Required profile

• 10+ years of ASIC/UVM verification experience.
• Strong analytical mindset and problem‑solving abilities.
• Excellent communication and collaboration skills.
• Proactive, self‑motivated, and able to work in fast‑paced environments.

Required skills

• UVM methodology
• SystemVerilog
• C, Python, TCL, Perl
• SVA and formal verification techniques
• Industry‑standard EDA tools for verification
• High‑Performance Interface IP protocols
• ASIC digital design and RTL knowledge