SRAM Design Lead / Architect (Advanced Node)

About the role

We are seeking a principal‑level SRAM Design Lead to own the architecture and delivery of custom embedded memory on our most advanced process node. You will drive the full design flow from specification through tape‑out, balancing area, power, speed, and yield while navigating aggressive variation and leakage constraints.

Key responsibilities

• Define SRAM architecture, including bit‑cell selection, array organization, redundancy scheme, and PPA targets.
• Make trade‑off decisions between density, speed, power, and yield for bleeding‑edge nodes.
• Coordinate circuit, layout, verification, and DFT teams to keep projects on schedule.
• Own memory compiler or hard‑macro generation strategy for configurable instances.
• Interface directly with foundry PDK and DTCO teams on process‑specific constraints.
• Review and sign off critical design decisions, corner cases, and tape‑out readiness.
• Set technical standards and mentor senior engineers on new node challenges.

Required profile

• 15+ years of analog/mixed‑signal or memory circuit design experience with multiple SRAM tape‑outs.
• Hands‑on experience designing SRAM at advanced FinFET or GAA/nanosheet nodes.
• Deep knowledge of bit‑cell physics, sense‑amp design, and failure modes under high variation and low‑voltage operation.
• Proven track record delivering custom memory from spec to silicon on a bleeding‑edge node.
• Strong expertise in yield and Monte‑Carlo analysis driving design margins.
• Direct experience working with foundry PDKs, including early‑stage or pre‑production versions.

Required skills

• SRAM architecture and bit‑cell design
• Analog/mixed‑signal circuit design
• Advanced FinFET and GAA/nanosheet node technologies
• Sensing amplifier design
• Yield analysis and Monte‑Carlo simulation
• Foundry PDK integration and DTCO collaboration
• Memory compiler tools (Synopsys, Cadence, or in‑house)