Memory Layout Design Engineer

About the role

Join Cisco’s Yerevan team as a Memory Layout Design Engineer. You will work on the Silicon One platform, implementing high‑quality SRAM memory layouts that power the world’s most advanced switches and routers.

Key responsibilities

• Design and implement SRAM block layouts meeting performance and reliability targets.
• Collaborate with international circuit design teams to translate schematics into physical designs.
• Run post‑layout simulations, resolve DRC issues and ensure clean integration with neighboring modules.
• Optimize layout for quality, visibility and delivery velocity.

Required profile

• Bachelor’s or Master’s degree in Electrical or Computer Engineering.
• 5+ years of professional experience in physical design or layout.
• 3+ years of hands‑on SRAM layout implementation.
• Experience with advanced nodes (TSMC 22nm, 12nm, 7nm, 5nm or 2nm).
• Proven ability to work independently and within a multi‑site, cross‑functional team.

Required skills

• EDA tools such as Cadence or Synopsys.
• EMIR/ERC closure and tape‑out support.
• Reading schematics, running circuit simulations.
• Scripting in Tcl, Python or Perl for design automation.

What we offer

• Hybrid work model (four days onsite in Yerevan).
• Opportunity to contribute to cutting‑edge silicon solutions for global networking.
• Collaboration with an international, high‑performance engineering team.