EMIR/ESD Engineer

About the role

Join Cisco's ASIC Physical Design Team to lead EMIR and ESD reliability analysis for next‑generation silicon. You will work across the full chip implementation flow, from RTL to GDSII, ensuring robust power grid performance and design integrity before tape‑out.

Key responsibilities

• Perform comprehensive chip‑level EMIR and ESD analysis and propose optimizations.
• Investigate complex EMIR/ESD results, collaborating with block owners and package teams to implement fixes.
• Coordinate with EDA tool vendors and flow teams to improve sign‑off methodology accuracy and scalability.
• Contribute to floorplanning, power planning, and overall physical implementation to meet performance and reliability targets.
• Support full‑chip physical design and tape‑out processes, ensuring readiness for production.

Required profile

• Bachelor's or Master's degree in Electrical Engineering or Computer Science.
• Minimum 3 years of hands‑on ASIC design and verification experience.
• Strong understanding of schematics and layout in FinFET and deep‑submicron CMOS technologies.
• Experience with RTL‑to‑GDSII flow, floorplanning, and power planning.

Required skills

• ASIC design and verification tools (Synopsys, Cadence, Siemens).
• EMIR and ESD protection concepts and implementation.
• Scripting languages: Python, TCL, Bash.
• Physical design concepts: floorplanning, power grid planning, tape‑out.

What we offer

• Opportunity to work on cutting‑edge silicon that powers global connectivity.
• Collaboration with world‑class engineers and cross‑functional teams.
• Access to advanced EDA tools and vendor support.
• Career growth within a leading technology company.