Senior Physical Design Engineer – Signoff Methodology

About the role

Join Cisco’s CAD Physical Design team within the Silicon One division, working from RTL to GDS in a hybrid setting (four days onsite at the Yerevan office). You will help evolve signoff methodologies for high‑performance, large‑scale chip designs.

Key responsibilities

• Develop and refine backend methodologies and flows from RTL to GDS, supporting high‑quality VLSI design.
• Advance signoff flows including physical synthesis, place‑and‑route, power optimization, timing closure, and physical closure.
• Collaborate with engineering teams to support and enhance implementation tool flows.
• Work with advanced silicon technologies and processes to deliver complex, reliable devices.

Required profile

• 5+ years experience as a CAD Physical Design Engineer (PnR and STA) or Design Engineer with strong backend design experience.
• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field.
• Strong understanding of STA flows and familiarity with physical verification and formal verification.

Required skills

• Physical design CAD tools (e.g., Synopsys, Cadence).
• Place‑and‑route (PnR) and static timing analysis (STA).
• Physical verification (PV) and formal verification (FV).
• Backend methodology development from RTL to GDS.