Technical Leader DFT & STA

About the role

Join Cisco's Silicon One Team, a cutting‑edge group developing advanced ASIC silicon architecture. As a Technical Leader DFT & STA you will define physical design methodologies, create robust flows, and work hands‑on with the physical design of complex chip partitions.

Key responsibilities

• Develop timing constraints at block, sub‑chip and full‑chip levels in test modes and perform quality checks such as duplicated constraints and promotion/demotion between block and top‑level SDCs.
• Validate SDCs, perform CDC delay checks, and develop SDC flow automation.
• Create methodologies, guidelines and checklists to streamline STA work, resolve design and flow issues, and ensure accurate execution.

Required profile

• Bachelor’s (or higher) degree in Electrical or Computer Engineering with 8+ years of relevant experience.
• Strong analytical skills, detail‑orientation and ability to communicate complex timing data across cross‑functional teams.
• Experience debugging and analyzing timing constraints for DFT modes such as scan shift/capture and BIST.

Required skills

• Static Timing Analysis (STA) tools, especially Synopsys PrimeTime.
• Block/full‑chip SDC development in test modes (scan shift, scan capture, ATPG capture).
• Programming/scripting in at least two of: Perl, TCL, Python, Makefile.
• Familiarity with Synopsys GCA/TCM, Fusion Compiler, and Tessent DFT insertion tools.