ASIC Physical Design Engineer

About the role

The ASIC Physical Design Engineer will lead macro‑level RTL‑to‑GDSII implementation for Cisco's Silicon One team, working on cutting‑edge hardware platforms for AI‑driven networking solutions.

Key responsibilities

• Perform synthesis, floorplanning, placement, clock‑tree synthesis and routing for complex SoCs.
• Optimize power, performance and area while ensuring design correctness through formal verification.
• Execute static timing analysis, physical verification, and sign‑off closure to deliver high‑quality silicon.
• Analyze and resolve electromigration and IR‑drop issues to meet reliability targets.

Required profile

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science or related field.
• 5+ years of hands‑on ASIC design and physical implementation experience.
• Proven track record on complex block‑level or SoC projects.

Required skills

• Deep knowledge of block‑level synthesis, place‑and‑route and timing closure.
• Experience with industry‑standard PnR and sign‑off tools such as Synopsys and Cadence.
• Proficiency in scripting languages (Tcl, Python, Perl) for automation.
• Familiarity with physical verification (LVS, DRC) and STA.