Senior RTL Design Engineer

About the role

Cisco’s Common Hardware Group in Yerevan is looking for a Senior RTL Design Engineer to join the Silicon One development team. You will work on high‑quality Design‑for‑Test verification for complex ASICs that power Cisco’s networking portfolio.

Key responsibilities

• Drive DFT verification and ensure robust silicon solutions that meet performance standards.
• Collaborate with front‑end RTL, back‑end physical design, and verification teams on micro‑architecture, RTL design, and qualification.
• Review and enhance RTL code, improve development flows, and support subsystem/SoC integration.
• Assist in complex debug sessions and interact closely with physical design to optimize QoR.

Required profile

• 5+ years of ASIC digital design experience.
• Proficient in Verilog/SystemVerilog coding and front‑end toolchains.
• Strong communication skills, self‑motivated and well‑organized.

Required skills

• Verilog and SystemVerilog.
• Python, Tcl, Make scripting.
• Experience with AMBA protocols (AXI, APB, AHB) and JTAG.
• Use of simulators, linting, CDC checkers, synthesis and formal verification tools.
• Familiarity with power optimization, UPF and DFT/MBIST concepts (a plus).