DDR I/O Analog and Mixed-Signal Design Intern

About the role

Synopsys, which designs high-performance silicon chips, is looking for an intern to join its DDR/LPDDR PHY and high-speed I/O circuit design team. You will work alongside experienced analog and mixed-signal circuit designers and receive mentorship from engineers, with hands-on exposure to production-level PHY development.

Key responsibilities

• Assist with transistor-level design and simulation of DDR I/O circuits.
• Analyze timing, power, signal integrity and PVT variations.
• Contribute to the design and functional verification of TX, RX, clocking, calibration and power-delivery circuits.
• Develop simulation testbenches and automate result analysis.
• Debug schematic, layout and post-layout simulation results.
• Document technical findings and present them to the design team.

Required profile

• Currently pursuing a BS or MS in Electrical Engineering or a related discipline.
• Coursework in analog/mixed-signal IC design, CMOS circuits or VLSI.
• Understanding of MOS device operation and basic circuit analysis.
• Strong analytical, debugging and communication skills; good written and spoken English, including technical documentation.

Required skills

• Familiarity with SPICE simulation.
• Scripting with Python, Perl, Tcl or Shell.
• Knowledge of DDR, LPDDR or other high-speed interfaces is a plus.
• Experience with Cadence or Synopsys custom-design tools, signal integrity, clocking circuits, statistical analysis or post-layout verification, and advanced-node CMOS design are all a plus.