Layout Design Manager

About the role

Lead a team of SRAM memory layout engineers to deliver embedded memories and memory compilers for advanced process nodes. Drive layout execution from floorplanning through physical verification sign‑off and product release.

Key responsibilities

• Lead SRAM layout development, including bitcells, arrays, peripheral circuits, power distribution networks and full memory instances.
• Resolve complex physical design challenges such as DRC, LVS, ERC, antenna, EM/IR, routing congestion and parasitic extraction across FinFET and GAA nodes.
• Manage project schedules, resource allocation, technical dependencies and risk mitigation for multiple concurrent memory compiler projects.
• Collaborate with circuit design, architecture, CAD tool, verification, process technology and foundry teams to align layout execution with product requirements.
• Build and improve layout methodologies, automation scripts, design‑reuse frameworks and standardization practices.
• Mentor engineers, conduct performance reviews, support hiring and onboarding, and grow the technical capability of the layout organization.

Required profile

• 7+ years of hands‑on SRAM memory layout experience, including bitcell and full‑memory integration.
• Deep understanding of SRAM architecture, memory compilers and how layout decisions impact performance, power, area, yield and reliability.
• Demonstrated experience leading engineering teams or managing complex technical projects with multiple stakeholders.
• Strong communication skills to translate vague requirements into concrete layout tasks and explain technical issues to both engineers and managers.

Required skills

• Proficiency with industry‑standard custom layout tools and physical verification flows.
• Expertise in DRC, LVS, ERC, antenna checks, EM/IR analysis and parasitic extraction.
• Experience with advanced‑node layout constraints for FinFET and GAA processes.
• Knowledge of layout automation and scripting (e.g., TCL, Python) is a plus.