Senior SOC Physical Design Engineer

About the role

Synopsys is looking for a Senior Staff SOC Engineer with expertise in ASIC physical design. The role leads block-level and chip-level physical design from netlist through final implementation, drives floorplan and optimization, and mentors junior engineers within a cross-functional team.

Key responsibilities

• Lead block-level and chip-level physical design from netlist through final implementation (RTL to GDSII)
• Drive floorplan: block shaping, power planning, pin and macro placement, special routing and ESD considerations
• Optimize placement, clock tree synthesis, post-CTS and routing for timing, power, area, congestion and signal integrity
• Perform signoff timing, EMIR and physical verification analysis and closure with ECOs
• Work with RTL, Implementation, DFT, packaging, foundation IPs and MBIST teams to reach hardening closure
• Develop and improve automation scripts and methodologies to raise physical design efficiency and quality
• Investigate and resolve design, tool, flow and machine issues throughout the implementation cycle
• Mentor junior engineers and provide technical leadership

Required profile

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related field
• Strong experience in ASIC physical design and implementation
• Experience with advanced process nodes and IP integration in complex SoCs
• Excellent written and verbal communication in English and ability to work in cross-functional teams
• Analytical, proactive, mentorship-oriented and adaptable

Required skills

• Full physical design flow, including floorplan, optimizations and signoff closure
• Strong understanding of STA, EMIR and physical verification
• Proficiency with Synopsys Fusion Compiler, PrimeTime, Redhawk SC, ICV and similar tools