Senior Circuit Design Engineer – Analog & Mixed‑Signal SRAM

About the role

We are looking for a senior circuit design engineer to lead the analog and mixed‑signal design of our custom SRAM core, including bitcells, sense amplifiers, write drivers, and peripheral logic on an advanced process node. You will collaborate closely with the design lead and layout team to meet aggressive power, speed, and area targets while handling tight noise margins and high variation.

Key responsibilities

• Design and simulate bitcell arrays, sense amplifiers, write drivers, and decoders using advanced‑node device models.
• Run corner and Monte Carlo simulations to validate margins across voltage, temperature, and process variation.
• Optimize circuits for power‑performance‑area (PPA) specifications in partnership with the design lead, addressing leakage and reduced voltage headroom.
• Work with layout engineers to resolve matching, parasitic, and floor‑plan challenges inherent to advanced geometries.
• Debug silicon bring‑up issues and correlate simulation results with measured data, focusing on new‑node effects.
• Document design decisions and maintain specifications throughout the project lifecycle.

Required profile

• 8+ years of analog/mixed‑signal circuit design experience, including SRAM or embedded memory design on advanced nodes.
• Hands‑on experience with FinFET or GAA/nanosheet devices and their short‑channel effects.
• Strong understanding of bitcell operation, sense‑amp topologies, and low‑voltage noise‑margin analysis.
• Proficiency in working across multiple PVT corners and interpreting Monte Carlo results at advanced‑node variation levels.

Required skills

• Analog/mixed‑signal circuit design
• SRAM/embedded memory design
• FinFET or GAA/nanosheet device modeling
• SPICE‑class simulation tools
• Statistical/variation‑aware simulation
• Monte Carlo analysis
• PVT corner analysis
• Silicon bring‑up debugging