Senior Circuit Design Engineer (ASIC)

About the role

Cisco Silicon One designs, develops and tests advanced ASICs for top-of-rack switches to web-scale data centers. As a Senior Circuit Design Engineer, you will own the end-to-end development of high-performance ASIC subsystems and reusable IP, working with architecture, physical design and silicon validation teams to optimize IP for next-generation networking silicon.

Key responsibilities

• Drive the architecture, design and implementation of ASIC subsystems and IP from specification through silicon validation.
• Develop and productize standard-cell, custom digital and analog/mixed-signal IP under strict performance and robustness requirements.
• Perform transistor-level simulation and optimization, accounting for process, voltage, temperature and aging conditions.
• Define and implement characterization methodologies for standard-cell and mixed-signal models, including automated EDA flows.
• Collaborate with physical design and system architecture teams on interface requirements and implementation constraints.
• Own the physical implementation of complex custom blocks, optimizing timing, power, signal integrity and layout-dependent effects.
• Analyze silicon results after bring-up to improve circuit design, characterization models and future IP architectures.
• Lead technical reviews of schematics, layouts and methodologies, and develop reusable scripts and documentation.
• Apply expertise in advanced process nodes such as FinFET and GAA.

Required profile

• Bachelor's degree with 7 years of related experience, or Master's degree with 4 years, or PhD with 1 year.
• Experience in ASIC, custom digital, standard-cell or analog/mixed-signal circuit design and implementation.
• Preferred: proven expertise in custom digital and analog/mixed-signal IP with a focus on PPA, reliability and yield.
• Preferred: first-hand experience with advanced nodes (FinFET/GAA) and physical implementation flows, including custom layout, parasitic extraction, DRC/LVS and reliability analysis.
• Preferred: demonstrated ability to lead technical reviews and influence ASIC architecture through silicon bring-up and failure analysis.

Required skills

• EDA tools from Cadence, Synopsys or Siemens; circuit-level analysis (SPICE, PVT, Monte Carlo, variation) and standard-cell modeling (Liberty, CCS/ECSM, LVF).
• Automation and scripting (Python, Tcl or shell).