Memory Layout Design Engineer

About the role

This hybrid position (four days per week on‑site) is based in Cisco’s Yerevan office. You will join an international team that designs memory layout for the Cisco Silicon One platform, powering advanced switches and routers.

Key responsibilities

• Implement high‑quality SRAM block layouts that meet strict performance and reliability targets.
• Collaborate with global circuit design teams to translate schematics into robust physical designs.
• Run post‑layout simulations, apply corrections, and ensure DRC cleanliness and proper integration with neighboring modules.
• Optimize layout quality, visibility, and delivery velocity to accelerate critical silicon components.

Required profile

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of professional experience in physical design or layout.
• Proven experience with industry‑standard EDA tools such as Cadence or Synopsys.
• Experience with advanced node technologies (e.g., TSMC 22nm, 12nm, 7nm, 5nm, or 2nm).

Required skills

• SRAM layout implementation.
• EMIR/ERC closure and tape‑out support.
• Circuit design reading and simulation.
• Scripting in Tcl, Python, or Perl for design automation.
• Advanced node technology knowledge (TSMC 22nm‑2nm).
• Cadence and Synopsys EDA tool proficiency.