Senior Circuit Design Engineer – Analog & Mixed‑Signal SRAM

About the role

We are seeking a senior circuit design engineer to lead the analog and mixed‑signal design of our custom SRAM core on a leading‑edge process node. The role involves creating bit‑cell arrays, sense amplifiers, write drivers and peripheral logic while meeting aggressive power, performance and area targets.

Key responsibilities

• Design and simulate bit‑cell arrays, sense amplifiers, write drivers and decoders using advanced‑node device models.
• Run corner and Monte Carlo simulations to validate margins across voltage, temperature and process variation.
• Optimize circuits for target PPA specifications in collaboration with the design lead, addressing leakage and reduced voltage headroom.
• Collaborate with layout engineers to resolve matching, parasitic and floor‑plan issues specific to advanced geometries.
• Debug silicon bring‑up problems and correlate simulation results with measured data, accounting for new‑node effects.
• Document design decisions and maintain specifications throughout the project lifecycle.

Required profile

• 8+ years of analog/mixed‑signal circuit design experience, including SRAM or embedded memory design on advanced nodes.
• Hands‑on experience with FinFET or GAA/nanosheet devices and their short‑channel effects.
• Strong understanding of bit‑cell operation, sense‑amp topologies and low‑voltage noise‑margin analysis.
• Proficiency with SPICE‑class simulators and statistical/variation‑aware design flows.
• Ability to work across multiple PVT corners and interpret Monte Carlo results at advanced‑node variation levels.

Required skills

• Analog circuit design
• Mixed‑signal circuit design
• SRAM design
• FinFET device modeling
• GAA/nanosheet device modeling
• SPICE simulation
• Statistical/variation‑aware simulation
• Monte Carlo analysis
• Corner analysis