Senior Staff Engineer – Analog Design

About the role

Synopsys is seeking an experienced analog and mixed‑signal engineer to lead the design of critical circuit blocks for next‑generation high‑speed connectivity IP, including PCIe Gen7/Gen8, AI accelerators and networking platforms.

Key responsibilities

• Design and deliver analog and mixed‑signal blocks such as PLLs, CDRs, equalizers, ADCs, DACs and clocking systems for high‑speed SerDes and PHY products.
• Perform architecture exploration, trade‑off analysis and transistor‑level optimization focusing on performance, power, jitter and signal integrity.
• Provide technical mentorship to engineers on circuit analysis, layout considerations and debugging methodologies.
• Collaborate with layout, verification, digital and system teams to ensure successful integration of mixed‑signal subsystems.
• Support silicon bring‑up, characterization and root‑cause analysis in coordination with lab and customer engineering teams.

Required profile

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related field.
• Minimum 10 years of professional experience delivering complex analog and mixed‑signal ICs through silicon validation.
• Proven ability to resolve complex circuit and system‑level challenges independently and influence technical direction.
• Experience with silicon bring‑up, characterization and debug activities is highly valued.

Required skills

• Analog and mixed‑signal IC design (PLL, CDR, equalization, ADC, DAC, clocking).
• High‑performance SerDes and PHY design, including PCIe Gen7/Gen8.
• Transistor‑level design, simulation, noise analysis, jitter budgeting and signal‑integrity optimization.
• Power optimization and area‑efficient layout techniques.
• Silicon bring‑up, characterization, and debugging methodologies.