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Senior Staff Engineer – ASIC Digital Design Verification

Synopsys Inc · Erevan

New
Senior 🇬🇧 English
UVM SystemVerilog Python TCL Perl SVA formal verification EDA tools

Job description

About the role

Synopsys is seeking an experienced ASIC Digital Design Verification Engineer to lead verification of complex ASIC blocks and systems. The role involves collaborating with design teams, building UVM testbenches, and ensuring high‑performance, reliable silicon.

Key responsibilities

  • Lead verification of complex ASIC blocks, defining verification requirements with design teams.
  • Build and maintain UVM testbenches, agents, and comprehensive test plans.
  • Apply SVA, formal verification, and coverage analysis to validate functionality and performance.
  • Utilize advanced EDA tools to optimize design performance and power efficiency.

Required profile

  • 10+ years of ASIC/UVM verification experience.
  • Proactive, self‑motivated engineer with strong analytical and problem‑solving abilities.
  • Excellent communication and collaboration skills across cross‑functional teams.

Required skills

  • UVM methodology and SystemVerilog.
  • Programming in C, Python, TCL/Perl.
  • SVA and formal verification techniques.
  • Experience with industry‑standard EDA verification tools.

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Published 3 ժամ առաջ

Expires 1 ամիսից

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Synopsys Inc

Erevan

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