Staff ASIC Digital Design Engineer

About the role

Synopsys is seeking an experienced ASIC Digital Design Staff Engineer to create high‑quality RTL for silicon IP blocks. You will work on real IP that ships in products used worldwide, ensuring designs are synthesis‑ready, timing‑aware, and meet CDC and lint requirements.

Key responsibilities

• Design and implement RTL for digital blocks and subsystems using Verilog/SystemVerilog.
• Refine micro‑architecture with focus on synthesizability, timing, testability, area, and power trade‑offs.
• Drive synthesis and front‑end implementation activities and support CDC/RDC/Lint sign‑off.
• Collaborate with implementation teams on STA fundamentals, timing constraints, and timing arc analysis.
• Work with verification teams on functional debug, test planning, assertions, and coverage.
• Debug issues using Verdi or similar tools and participate in design reviews.
• Develop automation scripts for design, debug, reporting, and productivity.

Required profile

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 4+ years of experience in digital design and RTL development.
• Strong background in synthesis, front‑end implementation, and design‑for‑closure methodology.
• Practical understanding of the ASIC design flow and STA concepts.

Required skills

• Verilog / SystemVerilog
• ASIC design flow
• Synthesis and front‑end implementation
• Static timing analysis (STA) and timing constraints
• Clock domain crossing (CDC) and reset domain crossing (RDC) awareness
• Lint sign‑off readiness
• Debug tools such as Verdi
• Scripting for automation (e.g., Tcl, Python)