Memory Layout Technical Leader

About the role

Join a cutting‑edge team that defines memory layout for Cisco Silicon One, the platform behind the world’s most advanced switches and routers. This hybrid position combines on‑site collaboration in Yerevan with remote work, offering the chance to shape high‑performance silicon that powers global networking infrastructure.

Key responsibilities

• Drive physical‑design strategy for high‑performance memory and SRAM blocks, aligning with aggressive power, performance and area targets.
• Architect complex layout solutions and provide technical leadership to raise team proficiency.
• Execute post‑layout validation cycles to ensure silicon‑level reliability and seamless integration across multi‑module subsystems.
• Lead enhancements to layout‑automation frameworks, reducing design iteration time and increasing overall velocity.
• Collaborate with cross‑functional teams to resolve EM/IR closure bottlenecks and support mixed‑signal/custom design environments.

Required profile

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or a related field.
• 10+ years of professional experience in physical design or layout, with at least 3 years focused on SRAM layout implementation.
• Proven ability to mentor and guide teams through complex project lifecycles.
• Strong analytical problem‑solving skills and experience influencing stakeholders in a global, multi‑site environment.

Required skills

• Expert‑level proficiency with industry‑standard EDA tools such as Cadence or Synopsys.
• Hands‑on experience with advanced node technologies (TSMC 22nm, 12nm, 7nm, 5nm, 2nm).
• Automation scripting expertise in Tcl and Python.
• Deep knowledge of SRAM layout, physical design, and EM/IR closure techniques.

What we offer

• Hybrid work model (four days onsite in Yerevan).
• Opportunity to work on industry‑leading silicon that powers next‑generation networking hardware.
• Collaborative, international team environment with a focus on technical excellence.