ASIC Design Verification Technical Leader

About the role

Join Cisco's Yerevan office in a hybrid capacity to lead a team focused on robust test infrastructure for cutting‑edge ASIC hardware. You will work closely with design and product development groups to integrate and validate test logic throughout the product lifecycle.

Key responsibilities

• Drive comprehensive test planning and develop advanced SystemVerilog test benches to ensure design integrity.
• Collaborate with cross‑functional teams to integrate and validate test logic at every implementation phase.
• Utilize scripting (Tcl, Python, Perl) and debugging tools (DVE, Verdi) to streamline verification workflows and quickly identify issues.
• Optimize test processes, apply constrained‑random verification and functional coverage, and deliver verification solutions that directly impact product quality and reliability.

Required profile

• Bachelor’s or Master’s degree in Electrical or Computer Engineering.
• 7+ years of experience in ASIC design verification and test planning.
• Strong analytical, problem‑solving and communication skills.
• Proven ability to work effectively in cross‑functional teams.

Required skills

• SystemVerilog and UVM expertise.
• Proficiency in scripting languages: Tcl, Python, Perl.
• Debugging experience with DVE and Verdi.
• Knowledge of constrained‑random verification, functional coverage, ASIC design flow, JTAG protocol and SLM IP verification strategies.