ASIC Engineering Technical Leader
cisco
Job description
About the role
This hybrid position is based four days a week at Cisco’s Yerevan office, joining the Silicon One team that drives cutting‑edge ASIC design for advanced process nodes.
Key responsibilities
- Define innovative physical‑design methodologies and create robust flows for complex chip development.
- Work on digital design from micro‑architecture to RTL, subsystem/SoC integration, and verification.
- Review and enhance RTL code, improve IP/SoC development flows, and collaborate closely with verification and physical‑design teams.
Required profile
- 8+ years of industry experience in ASIC digital design.
- Proficient in Verilog/SystemVerilog coding and front‑end tools (simulators, linting, CDC checkers, synthesis, formal verification).
- Strong communication skills, self‑motivated and well‑organized.
Required skills
- Verilog / SystemVerilog
- Front‑end design tools (simulation, lint, CDC, synthesis, formal)
- AMBA protocols (AXI, APB, AHB), JTAG, memory interfaces
- Scripting in Python, Tcl, Make
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