Standard Cells Characterization Engineer

About the role

Join Cisco's Common Hardware Group to lead the end‑to‑end characterization flow for standard cell libraries, supporting cutting‑edge ASIC development for networking hardware.

Key responsibilities

• Lead characterization from extracted netlists through Liberty delivery and correlate against TSMC reference data.
• Define and maintain PrimeLib/Liberate methodology, templates, and automation for timing, power, noise, and leakage across PVT and RC corners.
• Own extraction‑to‑characterization integration, including LVS/StarRC setup, RC corner alignment, well‑bias handling, and netlist quality gates.
• Debug failures at netlist, simulation, and Liberty‑model levels and develop reusable Tcl/shell flows and documentation.
• Partner with library design, physical verification, and CAD teams to ensure cell readiness and drive sign‑off criteria.

Required profile

• Bachelor's in EE/CS with 6 years experience (or equivalent higher degree with fewer years).
• Hands‑on experience characterizing standard cell libraries using PrimeLib, Liberate, or similar tools.
• Strong understanding of Liberty formats, TSMC (or equivalent) characterization flows, and parasitic extraction.
• Solid knowledge of CMOS device behavior, timing arcs, power domains, and well/substrate bias effects.

Required skills

• PrimeLib / Liberate characterization tools
• Liberty NLDM, CCS, noise and leakage modeling
• TSMC (or equivalent) characterization flow knowledge
• StarRC or equivalent parasitic extraction, LVS
• Tcl, Perl, Python scripting for automation