Senior ASIC Digital Design Engineer - UCIe Controller IP

About the role

Synopsys is looking for an ASIC digital designer to design RTL modules for the UCIe Controller IP, which is used in high-performance computing applications. The role takes RTL modules from specification through implementation into production silicon, working closely with architecture, verification and physical design.

Key responsibilities

• Design and own RTL modules for the UCIe Controller IP, from microarchitecture through synthesis-ready implementation, with guidance from senior designers
• Tune modules to meet timing, power and area targets, using feedback from synthesis and timing analysis across process nodes
• Develop Python, Tcl and Perl scripts for design generation and flow integration
• Take part in design reviews and contribute improvements to team methodology

Required profile

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related field
• 2-3 years of ASIC digital design experience, including ownership of RTL modules in production or near-production silicon
• Experience with controller IP or high-speed interfaces is preferred

Required skills

• Strong Verilog skills for timing-critical designs
• Working proficiency in Python, Tcl or Perl for design automation
• Hands-on experience with synthesis, static timing analysis and power optimization
• Ability to connect RTL structure to timing and power results and to communicate clearly with architects, verification and physical design engineers