ASIC DFT DV Technical Leader

About the role

This hybrid position is based at Cisco’s Yerevan office, leading the development and execution of test benches to verify DFT architectures for silicon devices. You will collaborate across design, verification, and product teams to ensure robust test coverage and post‑silicon validation.

Key responsibilities

• Lead creation and execution of comprehensive test benches for DFT verification.
• Integrate test logic across implementation stages and post‑silicon validation flows.
• Drive hardware DFT innovation and reusable test methodologies for new silicon models.
• Mentor junior engineers and guide solution brainstorming for DFT challenges.

Required profile

• Bachelor’s or Master’s in Electrical/Computer Engineering or related field.
• 10+ years of experience in design verification or ASIC design.
• Proven experience in test planning based on complex specifications.
• Strong problem‑solving ability with minimal supervision.

Required skills

• Proficiency with DVE/Verdi debugging tools.
• Scripting in Tcl, Python, or Perl.
• Testbench development using SystemVerilog.
• Knowledge of JTAG, scan architecture, MBIST, and boundary‑scan.