Senior STA Timing Engineer

About the role

Join Cisco's Test Timing Engineering team to develop and validate timing constraints for advanced chip designs. You will ensure robust and accurate timing across block, sub‑chip, and full‑chip levels in various test modes, contributing directly to product quality.

Key responsibilities

• Own creation and validation of timing constraints at multiple hierarchy levels and test modes.
• Perform quality checks to identify duplicated constraints and verify unconstrained endpoints.
• Develop methodologies, guidelines, and checklists to streamline static timing analysis (STA) workflows.
• Collaborate with cross‑functional teams to resolve timing and design flow issues.
• Implement and maintain SDC flows and validation processes across design stages.

Required profile

• Bachelor’s degree in electrical or computer engineering with 8+ years experience, or Master’s with 6+ years.
• Proven experience developing block/full‑chip SDC in test modes (scan shift, scan capture, ATPG capture).
• Strong communication skills and ability to work collaboratively in cross‑functional teams.

Required skills

• Static Timing Analysis (STA) tools, especially Synopsys PrimeTime.
• Scripting languages: Perl, TCL, Python, Makefile.
• SDC validation, timing exception handling, and STA flow development.
• Experience with Synopsys GCA/TCM/PrimeTime and Fusion Compiler.
• Familiarity with Tessent DFT insertion tools.